As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 19, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
In order to properly accomplish such tasks, the computer system 10 relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator 18 generates a system clock signal (referred to and known in the art as xe2x80x9creference clockxe2x80x9d and shown in FIG. 1 as sys_clk) to various parts of the computer system 10. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor 12 and the other components of the computer system 10 use a proper and accurate reference of time.
One component used within the computer system 10 to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., xe2x80x9cchip clock,xe2x80x9d is a type of clock generator known as a phase locked loop, or xe2x80x9cPLLxe2x80x9d 20. The PLL 20 is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to FIG. 1, the PLL 20 has as its input the system clock, which is its reference signal, and outputs a chip clock signal (shown in FIG. 1 as chip_clk) to the microprocessor 12. The system clock and chip clock have a specific phase and frequency relationship that is controlled and maintained by the PLL 20. This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor 12 use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL 20, however, the operations within the computer system 10 may become non-deterministic.
FIG. 2 shows a diagram of a typical PLL 30. The PLL 30 uses a phase frequency detector 36 that operatively receives an input clock signal, clk_in 32, and a feedback clock signal, fbk_clk 34. The phase frequency detector 36 compares the phases of the input clock signal 32 and the feedback clock signal 34, and dependent on the comparison, the phase frequency detector 36 outputs pulses on UP 38 and DOWN 40 signals to a charge pump 42. Depending on the pulses on the UP 38 and DOWN 40 signals, the charge pump 42 transfers charge to or from a loop filter capacitor 46 via a voltage control signal, Vctrl 45. Those skilled in the art will understand that the loop filter capacitor 46 along with a loop filter resistor 44 form a xe2x80x98loop filterxe2x80x99 of the PLL 30.
The voltage control signal 45 serves as an input to a bias generator 50, which, in turn, outputs at least one bias signal 51 to a voltage-controlled oscillator 52. The voltage-controlled oscillator (VCO) 52, dependent on the at least one bias signal 51, outputs a clock signal, clk_out 60, that (1) propagates through a clock distribution network 54 (modeled in FIG. 2 as buffers 56 and 58) and (2) serves as an output of the PLL 30. The output clock signal 60 is fed back through a feedback divider 62, which, in turn, outputs to a buffer 64 that generates the feedback clock signal 34 to the phase frequency detector 36. For a more detailed background on the operation and behavior of a PLL, see J. Maneatis, xe2x80x9cLow-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,xe2x80x9d IEEE Journal of Solid-State Circuits, vol. 31, no. 11, November 1996.
According to one aspect of the present invention, an integrated circuit comprises: a phase frequency detector arranged to detect a phase difference between a first clock signal and a second clock signal; a charge pump arranged to output a voltage control signal dependent on the phase difference; a capacitor operatively connected to the voltage control signal; a leakage control circuit operatively connected to the capacitor and a voltage potential, wherein the leakage control circuit comprises a switch responsive to the phase frequency detector; and a voltage-controlled oscillator arranged to output the second clock signal dependent on the voltage control signal.
According to another aspect, an integrated circuit comprises: means for detecting a phase frequency difference between a first clock signal and a second clock signal; means for generating a signal dependent on the phase frequency difference; means for storing charge to maintain a voltage potential on the signal; a switch arranged to control a leakage current of the means for storing charge dependent on the means for detecting the phase frequency difference; and means for generating the second clock signal dependent on the signal.
According to another aspect, a method for performing a phase locked loop operation comprises: comparing a phase difference between a first clock signal and a second clock signal; generating a voltage control signal dependent on the comparing; storing charge dependent on the voltage control signal using a capacitor; controlling a leakage current of the capacitor with a switch positioned in series with the capacitor, wherein the switch is responsive to the comparing; and generating the second clock signal dependent on the voltage control signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.